isa1 properties: 16 bit instructions 8 registers 3 address ops no condition bits load/store addressing modes: ,[] ,[,#imm] ,[,#imm]+ ,[PC,#imm] # only on load ldr str load immediate li ,#immediate # 10 bits of immediate, sign extended 3 address data processing: two forms ,, - ,,#immediate (3 bits) add sub and or xor lsl lsr rol ror asr conditional branch bnz , bz , branch b b bl # modifies r7 system instructions mov to/from control register, 8 bits of control register swi? 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 add 0 0 0 0 0 0 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd # 3 bits of immediate sub 0 0 0 0 0 1 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd and 0 0 0 0 1 0 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd or 0 0 0 0 1 1 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd xor 0 0 0 1 0 0 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd lsl 0 0 0 1 0 1 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd lsr 0 0 0 1 1 0 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd asr 0 0 0 1 1 1 I Rb/imm Rb/imm Rb/imm Ra Ra Ra Rd Rd Rd li 0 0 1 imm imm imm imm imm imm imm imm imm imm Ra Ra Ra # 10 bits of immediate (sign extended) ldr 0 1 0 0 0 imm imm imm imm imm Ra Ra Ra Rd Rd Rd # ,[,#imm] ldr 0 1 0 0 1 imm imm imm imm imm Ra Ra Ra Rd Rd Rd # ,[,#imm]+ - update the base register ldr 0 1 0 1 0 0 0 Rb Rb Rb Ra Ra Ra Rd Rd Rd # ,[,] unused 0 1 0 1 0 0 1 X X X X X X X X X unused 0 1 0 1 0 1 X X X X X X X X X X ldr 0 1 0 1 1 imm imm imm imm imm imm imm imm Rd Rd Rd # ,[PC,#imm] - 8 bits of PC offset str 0 1 1 0 0 imm imm imm imm imm Ra Ra Ra Rd Rd Rd # ,[,#imm] str 0 1 1 0 1 imm imm imm imm imm Ra Ra Ra Rd Rd Rd # ,[,#imm]+ - update the base register str 0 1 1 1 0 0 0 Rb Rb Rb Ra Ra Ra Rd Rd Rd # ,[,] unused 0 1 1 1 0 0 1 X X X X X X X X X unused 0 1 1 1 0 1 X X X X X X X X X X b 0 1 1 1 1 0 0 0 0 0 0 0 0 Ra Ra Ra # branch to register unused 0 1 1 1 1 1 X X X X X X X X X X bnz 1 0 0 off off off off off off off off off off Ra Ra Ra # 9 bits of branch bz 1 0 1 off off off off off off off off off off Ra Ra Ra b 1 1 0 0 off off off off off off off off off off off off # 12 bits of branch bl 1 1 0 1 off off off off off off off off off off off off # 12 bits of branch system instructions: lmr 1 1 1 0 0 cr cr cr cr cr cr cr cr Rd Rd Rd # Rd, cr - load from cr smr 1 1 1 0 1 cr cr cr cr cr cr cr cr Rd Rd Rd # Rd, cr - store to cr expansion space 1 1 1 1 X X X X X X X X X X X X